1. Field of the Invention
The present invention relates to a p-channel MOS transistor that is strained to improve operation speed and a semiconductor integrated circuit device including such a p-channel MOS transistor.
2. Description of the Related Art
Owing to the development of micro-fabrication technology, presently, a super miniaturized super high-speed semiconductor device having a gate length less than 100 nm can be fabricated.
In such a super miniaturized super high-speed transistor, the area of a channel region right below a gate electrode is significantly smaller than that of a conventional semiconductor device so that electron mobility or hole mobility at such a channel region may be greatly influenced by stress applied to this channel region. Accordingly, techniques have been proposed for optimizing the stress applied to such a channel region to improve the operation speed of a semiconductor device.
FIGS. 1A and 1B are diagrams respectively illustrating ideal stress distributions for improving the operation speed of an n-channel MOS transistor and a p-channel MOS transistor according to Ota, K., et al. (see below Non-Patent Reference 7).
In the n-channel MOS transistor shown in FIG. 1A, an n-type polysilicon gate electrode 3N is arranged across a device region 1N, and the device region 1N is divided into an n-type source region S and an n-type drain region D by the polysilicon gate electrode 3N.
Similarly, in the p-channel MOS transistor shown in FIG. 1B, a p-type polysilicon gate electrode 3P is arranged across a device region 1P, and the device region 1P is divided into a p-type source region S and a p-type drain region D by the polysilicon gate electrode 3P.
In the n-channel MOS transistor of FIG. 1A, electron mobility at the channel region located right below the gate electrode 3N may be increased and the transistor operation speed may be improved when tensile stress (in-plane tensile stress) is applied in the gate width directions and the gate length directions. In the p-channel MOS transistor of FIG. 1B, hole mobility at the channel region located right below the gate electrode 3P may be increased and the transistor operation speed may be improved when tensile stress is applied in the gate width directions and compression stress (uniaxial compression stress) is applied in the gate length directions.
FIG. 2A is a diagram showing one exemplary n-channel MOS transistor structure according to the prior art that has been proposed for inducing tensile stress acting in the gate length directions as shown in FIG. 1A at the channel region right below the gate electrode 3N.
In the n-channel MOS transistor shown in FIG. 2A, a device region 1N is defined within a silicon substrate 1, and an n+-type polysilicon gate electrode 3N is formed on the silicon substrate 1 within this device region 1N via a gate insulating film 2N. Also, an n-type source extension region 1aN and an n-type drain extension region 1bN are formed at the sides of the polysilicon gate electrode 3N within the portion of the silicon substrate 1 corresponding to the device region 1N.
Also, sidewall insulating films 4nN made of SiN are formed on the sidewalls of the polysilicon gate electrode 3N via sidewall oxide films 4oN, and an n+-type source region 1cN and an n+-type drain region 1dN are formed at side portions of the silicon substrate 1 located further outward from the sidewall insulating films 4nN.
Also, silicide films 5SN, 5DN, and 5GN are formed on the n+-type source region 1cN, the n+-type drain region 1dN, and the n+-type polysilicon gate electrode 3N, respectively. Additionally, a SiN film 6N that stores tensile stress is arranged on the silicon substrate 1 to cover the silicide films 5SN, 5DN, 5GN and the sidewall insulating films 4nN.
The tensile stress stored in the SiN film 6N acts to push the gate electrode 3N toward the silicon substrate 1 in a direction perpendicular to the substrate surface. As a result, strain is induced at the channel region right below the gate electrode 3N which strain is similar to the strain induced when tensile stress is applied in the gate length directions as is shown in FIG. 1A.
FIG. 2B is a diagram showing an exemplary p-channel MOS transistor structure disclosed in Pidin, S., et al. (see below Non Patent Reference 6) for inducing compression stress acting in the gate length directions as shown in FIG. 1B at a channel region right below a gate electrode.
In the p-channel MOS transistor shown in FIG. 2B, a device region 1P is defined on a silicon substrate 1, and an p+-type polysilicon gate electrode 3P is formed on this device region 1P via a gate insulating film 2P. Also, a p-type source extension region 1aP and a p-type drain extension region 1bP are formed at the sides of the polysilicon gate electrode 3P within the portion of the silicon substrate 1 corresponding to the device region 1P.
Also, sidewall insulating films 4nP made of SiN are formed on the sidewalls of the polysilicon gate electrode 3P via sidewall oxide films 4oP, and an n+-type source region 1cP and an n+-type drain region 1dP are formed at side portions of the silicon substrate 1 located further outward from the sidewall insulating films 4nP.
Also, silicide films 5SP, 5DP, and 5GP are formed on the n+-type source region 1cP, the n+-type drain region 1dP, and the n+-type polysilicon gate electrode 3P, respectively. Additionally, a SiN film 6aP that stores compression stress is arranged on the silicon substrate 1 to extend over the silicide films 5SP, 5DP, 5GP and the sidewall insulating films 4nP.
The compression stress stored in the SiN film 6P acts to pull the gate electrode 3P away from the silicon substrate 1 in a direction perpendicular to the substrate surface. As a result, strain is induced at the channel region right below the gate electrode 3P which strain is similar to the strain induced when compression stress is applied in the gate length directions as is shown in FIG. 1B.
However, when the n-channel MOS transistor and the p-channel MOS transistor as shown in FIGS. 2A and 2B are fabricated on the same substrate to create a CMOS device, for example, the tensile stress film 6N and the compression stress film 6P have to be separately fabricated so that the fabrication process may become complicated.    [Patent Reference 1]: Japanese Laid-Open Patent Publication No. 2003-86708    [Patent Reference 2]: WO2002/043151    [Non-Patent Reference 1]: Shimizu, A., et al., IEDM Technical Digest, p. 433, 2001    [Non-Patent Reference 2]: Nakahara, Y., et al., IEDM Technical Digest, p. 281, 2003    [Non-Patent Reference 3]: Chen, C., et al., 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 56-57    [Non-Patent Reference 4]: Ghani, T., et al., IEDM 2003, pp. 978-980, Jun. 10, 2003    [Non-Patent Reference 5]: Oishi, A., et al., IEDM 2005, pp. 229-232    [Non-Patent Reference 6]: Pidin, S., et al., IEDM Technical Digest p. 213, 2004    [Non-Patent Reference 7]: Ota, K., et al., 2005 Symposium on VLSI Technology Digest of Technical Papers pp. 138-139